Enhancing Trace Generation-based Software Debugging Infrastructure for Physical and Emulated Development Platforms

Software debugging is now widely reported to constitute the majority of software development time and cost, largely due to the effects of continuously rising software complexity. In a trend which is expected to continue, complex software faults that can require weeks to resolve are becoming increasingly commonplace. Since traditional debugging methods are considered unsuitable for resolving such faults, trace generation is being recognized as a solution to future debugging needs. This thesis presents trace generation infrastructure that includes advanced on-chip supporting hardware, complementary software tools, and interfaces to bridge the gap between them. The contributions enable or enhance the use of trace generation across a variety of software development platforms. Even though embedded software development is increasingly performed on software emulators, many existing emulators lack trace generation capabilities. This thesis provides the ubiquitous QEMU emulator with the ability to perform trace experiments. The described extensions enable continuous instruction-level trace generation to be controlled using a standard software debugger client, which is given the ability to create tracepoints to dynamically log registers and memory addresses. The infrastructure is made aware of operating system context-switching in a unique way, which allows traces to be collected in five different modes: from all executed code, down to a single Linux process. For hardware-based development platforms, the volume of on-chip trace data generated in real-time can exceed the ability to practically transfer or store it. This thesis presents two different schemes for the compression of execution traces, which are vital in establishing the flow of software execution post-hoc. The Architecture-Aware Trace Compression (AATC) scheme eliminates previously unidentified redundancies within typical execution traces using a combination of on-chip predictors, transforms, and encoders. The scheme achieves the highest-performance compression of any similar method, most notably by exploiting the widespread use of linked branches, as well as the compiler-driven movement of return addresses between link-register, stack, and program counter. The Multi-Architectural Trace Compression (MATC) scheme is also introduced to compress the execution traces of any fixed instruction-width soft-core processor deployed on Field-Programmable Gate Array (FPGA) platforms. A novel architecture is presented in which five parameterizable variants of a pipelined scheme allow different combinations of unused logic and memory resources to be repurposed for trace compression purposes.